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Standard on Device Embedded Substrate Terminology / Reliability Test / Design Guide – Edition 4 –

  • JPCA-EB01-2011
  • 2011年 6月 第4版 第1刷発行
  • A4判 198ページ


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Process of preparation of this standard

The first edition of JPCA-EB01 was prepared by the JPCA Embedded Device Standardization Committee in 2008 to cover the basics of embedded device board technology covering concept of device embedding, structure, test methods, specification and product quality. This edition included very basics of the technology in the concept partly based on JIS C 5012 – Test methods of printed wiring board, a document prepared based on a JPCA document. The document was revised every year for the second edition in 2009 and the third edition in 2010 together with cooperation of the EPADs Study Group (Embedded Passive and Active Devices) of JIEP (Japan Institute of Electronic Packaging). These editions included design of TEG as a dummy chip for embedded device tests, drop test, vibration test and bending of device embedded board. The present 4th edition is prepared employing the information included in JPCA-PB02 – Printed wiring board. The present edition includes embedding of semiconductor bare dies and micro-integrated passive components as the use of module substrate, classification of print wiring board, together with additional information on new product specifications which are of importance to new products.

(Note added in proof: The second edition of JPCA-EB01 was submitted to IEC (International Electrotechnical Commission) TC91 – Technical Committee in Electronics Assembly Technology in 2009 to be prepared as an international standard in 2009, as a PAS (Publically available information) and NP (New work proposal). PAS has been published in 2010 as an official publication of IEC as a technical information source, and NP was also approved and now in process of bringing it to an international standard. IEC TC91 has organized a new WG (working group) to discuss this specific technology in 2009 with Convenor by a member of JPCA. EB01 has been also introduced to meetings of JIC (JISSO International Commission) and to IPC in the US. EB01 has been known around the world as a new technology information source by experts in electronics technology.)

Contents
1. Scope
1.1 Scope of product
1.2 Scope of technology involved
1.2.1 Base
1.2.2 Embedded Devices
1.2.3 Mounting and Interconnections
1.2.4 Fabrication Process
2. Structure and Terminology
2.1 Interconnections and Structure of the Device Embedded Board
2.2 Naming of Each Section
3. Test Condition and Sample Preparation
3.1 Test Condition
3.2 Test Specimens and Number of Specimens to be Used
3.3 Test Element Group (TEG)
3.3.1 Preparation of TEG
3.3.2 Structures of TEG
3.3.3 Test Pattern Guide
4. Test Methods
4.1 Visual Test and Micro-sectioning
4.1.1 Visual Test
4.1.2 Micro-Sectioning
4.2 Dimensional Tests
4.2.1 Dimensions
4.2.2 Thickness
4.2.3 Hole Diameter
4.2.4 Hole Position
4.2.5 Conductor Width and Minimum Conductor Width
4.2.6 Conductor thickness and wall plated film thickness
4.2.7 Lack of Conductor and Residue of Conductor
4.2.8 Land Dimension and Land Width (Annular Ring)
4.2.9 Solder Resist and Symbol Mark
4.2.10 Coplanarity
4.3 Electrical Tests
4.3.1 Resistivity
4.3.2 Withstanding Current
4.3.3 Withstanding Voltage
4.3.4 Insulation Resistance
4.3.5 Conduction and Insulation of Circuit
4.4 Mechanical Tests
4.4.1 Pulling Strength of Conductor
4.4.2 Pulling Strength of Un-plated Through Hole
4.4.3 Pulling Strength of Plated Through Hole
4.4.4 Pulling Strength of Pad of Land Pattern
4.4.5 Adhesivity of Plated Foil
4.4.6 Adhesivity of Solder Resist and Symbol Mark
4.4.7 Hardness of painted film l
4.5 Environmental Tests
4.5.1 High Temperature Test
4.5.2 Low Temperature Test
4.5.3 Thermal Shock (high and low temperatures)
4.5.4 Resistance to humidity
4.5.5 Resistance to Migration
4.6 Mechanical Environmental Test
4.6.1 Vibration
4.6.2 Drop Test
4.6.3 Bending
4.6.4 Screwing
4.7 Chemical Test
4.7.1 Flammability
4.7.2 Resistivity to Solvent
4.7.3 Solderability
4.7.4 Resistivity to Soldering Heat
4.7.5 Resistivity to Heat of Solder Resist and Symbol Mark
4.8. Other relevant standards
5. Specifications
5.1 Classifications of Products and Specification
5.1.1 Classification of Products
5.1.2 Classification of Specifications
5.2 Classification of Products and Allowance
5.2.1 Dimensions
5.2.2 Board Thickness
5.2.3 Through Hole
5.2.4 Fiducial Hole and Fiducial Mark
5.2.5 Conductor
5.2.6 Embedding Devices
5.2.7 Print Contact
5.2.8 Land pattern peripheral arrangement
5.2.9 Area array arranged land pattern
5.2.10 Land
5.2.11 Solder Resist and Symbol Mark
5.3 Display, package and storage
5.3.1 Display on product
5.3.2 Display on package
5.3.3 Package and storage
6. Quality inspection
6.1 Appearance
6.1.1 Hole and outer shape formation
6.1.2 V cut
6.1.3 Coplanarity
6.2 Conductor
6.2.1 Conductor gap
6.2.2 Deviation of conductor layers
6.2.3 Lack of conductor
6.2.4 Conductor left in conductor gap
6.3 Land
6.3.1 Minimum land width
6.3.2 Lack of land
6.3.3 Lack of land pattern in peripheral arrangement
6.3.4 Lack of land pattern in area array arrangement
6.3.5 Lack of print contact
6.4 Solder resist
6.4.1 Defects in solder resist
6.4.1-1 Position deviation of solder resist
6.4.1-2 Appearance of solder resist
6.5 Symbol Mark
6.6 Surface treatment
6.6.1 Nickel and gold plating
6.6.2 Other surface treatment
6.7 Appearance
6.7.1 Conductor surface and inner layer surface
6.7.2 Conductor gap
6.7.3 Defect in component mounting hole and via
6.7.4 Defect in insulating layer
7. Design Guide
7.1 Base and Specification for Assembly
7.2 Specification for Device Embedding and Assembly
7.3 Specification for Embedding Device
7.4 Design Specification
8. Terms used in this Document
9. Additional Information of this Document


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