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PURINTOBAN-JYUKU IV Introduction to Buid-up Printed Wiring board

  • By Tadashi Kobayashi
  • First Printing (Japanese Edition) April 1, 2001
  • First Printing of English Edition March 20, 2002
  • A5 Size 85 Pages


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Forwad

The PWB is the vehicle for the interconnection of devices and components of a very wide range from semiconductor LSI of super fine structures to human maneuverable devices like keyboards and switches. The build-up wiring board is a kind of PWBs and can be considered as a platform of high-density interconnection close to that used in semiconductor technology compared to conventional multilayer PWBs.
The build-up board technology has made a considerable development in the past decade but it is not yet a completed and matured technology. Various build-up processes have been proposed and in actual use in production now. But many new processes and techniques are still being proposed as new techniques of build-up board manufacturing. The development in the technology should be based not on the board manufacturing technology alone but on the requests from both semiconductor technology and the needs of system developers.
This book is prepared not to cover all the details of the present day technology of the build-up PWB manufacturing but to describe plainly the fundamentals of the build-up board technology. Efforts have been made to explain basics of the build-up technology including comparison with the conventional board technology in various aspects, measures to meet the requirements for mounting of rapidly progressing semiconductor devices and issues related to electrical characteristics of PWBs.
This book consists of the main text and notes. The key aspects of the technology are described in the main text and the details of some of important subjects are explained in notes. There are many cases in this book and also in some catalogues without precise explanation to use technical terms and idioms that are not defined yet by JIS and IEC documents. Efforts have been made in this book to use explicitly typical numbers in explanation to assist in understanding of the meaning of terms. Such numbers used in this book could be obsolete and may not be used in present day production lines. Readers are encouraged to confirm the numbers with the actual cases he/she may encounter in production.
This book is planned as to a continuation volume of the book “Introduction to the Printed Wiring Board Technology” I have written. The former book was intended for novice engineers who would face to the PWBs technology for the first time. This book is prepared for the engineers in this field with an assumption that he/she has basic understandings of the technology that is stated in t he previous book. Reference may be made to the previous book to renew understanding of the PWB fundamentals time to time.
Readers may not to try conquer the top of Mt. Fuji starting from 5-Gome area but may endevour to have an overview of the mountain (technology) from 3-Gome to 8-Gome area (3/10-th height to 8/10-th height) of the technology.

March 2002
Tadashi Kobayashi



Contents
1. Build-up PWB
1.1 Build-up Process
1.2 Why Build-up PWB Now?
1.3 Advantages and Disadvantages of Conventional Multilayer Process
1.4 Differences in the Conventional and Build-up Processes
2. Packaging of Semiconductor Devices and Electronic Equipment
2.1 Hierarchy of Packaging
2.2 High Element Density of IC Chips and Fine Wiring Pitch for Packaging
2.3 Trend in High-density Packaging and Shift of Multilayer Production Process toward Build-up Process
2.4 Electric Characteristics of PWB
2.5 Matching of Characteristic Impedance
3. Fabrication Process of Build-up PWB
3.1 Types of Fabrication Processes
3.2 Resin Coated Copper Foil (RCC) Process
3.3 Build-up Process using Photosensitive Resin
3.4 Build-up Process using Thermosetting Resin
3.5 Build-up Process using Conductive Paste
3.6 Total Layer Build-up PWB by Single Lamination
4. Process Flow, Quality Management and Reliability of PWB made by Build-up Process
4.1 Layer-to-layer Registration
4.2 Formation of Dielectric Layer
(1) Bond Strength of Conductor
(2) Thermal Expansion and Resin Crack
(3) Migration
(4) Heat Resistance
(5) Properties of Dielectric Resin
4.3 Mechanical Properties
4.4 Electrical Properties
4.5 Test and Inspection
4.6 Process Control
4.7 Design
4.8 Performance and Test Methods
(1) Standardization of Performance and Test Methods
(2) Issues in the Reliability Test
5. Position of Typical Build-up Processes in for PWB Fabrication and Subjects to be Considered
(1) Resin Coated Copper Foil (RCC) Process
(2) Photo-via Process
(3) Sequential Lamination Process and Single Lamination Process
6. Terminology
Conformal Via
Filled Via
Stacked Via
Skipped Via
Filled-Base Via
Stud Via
Via Trench
Acceleration Factor
Via-top Land (diameter) and Via-bottom Land (diameter)
Interposer
Transfer method
Low Profile Copper Foil
Interposer
Transfer method
Low Profile Copper Foil
References

Notes:
1.1 The Term “Build-up Process”
1.2 HDI
1.3 Thin Film Hybrid Circuit
1.4 Design Rule
1.5 Multilayer Structure and Cost Increase
1.6 Copper Clad Laminate (CCL)
1.7 Bond Strength (Peel Strength)
1.8 Panel Plating, Pattern Plating and Semi-additive Process
1.9 Side Etch and Final Conductor Width
1.10 Ceramic Multilayer PWB
1.11 Sequential Multilayer PWB
2.1 System
2.2 Rent’s Law
2.3 Fan-out
2.4 Flip-chip
2.5 Bare chip
2.6 QM (Quasi-module)
2.7 Peripheral Arrangement and Array Arrangement of Terminals
2.8 Three Dimensional Packaging
2.9 DC Resistance, Inductance, Capacitance and Impedance
2.10 Transmission Line and Characteristic Impedance
2.11 Reflection of Light and Transmission of Light
2.12 Calculation of Characteristic Impedance
3.1 Resin Coated Copper Foil (RCC)
3.2 Laser Drilling
3.3 Plasma Etching
3.4 Half Etching
3.5 Conformal Mask Method and Direct Drilling Method
3.6 Surface Treatment to very small Holes and Trenches (Developing, Etching and Plating)
3.7 Photosensitive Resin
3.8 Surface Roughening
3.9 Conductive Paste
3.10 Aramid Fiber Reinforced CCL
3.11 Bump
3.12 Via-on-Via (Stacked Via), Via-on-Pad and Pad-on-Hole
3.13 Interstitial Via and IVH (Blind Via and Buried Via)
4.1 Terminal Size, Solder Resist and Resin Crack
4.2 Short Rubber Method for Electrical Testing of Fine Conductor Pattern
4.3 Glass Transition Temperature
4.4 Cumulative Failure Rate and Normal Probability Plot
4.5 Fatigue Life of Build-up PWB

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